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? semiconductor components industries, llc, 2012 april, 2012 ? rev. 7 1 publication order number: ncv7420/d ncv7420 lin transceiver with 3.3v or 5 v voltage regulator general description the ncv7420 is a fully featured local interconnect network (lin) transceiver designed to interface between a lin protocol controller and the physical bus. the tran sceiver is implemented in i3t technology enabling both high ? voltage analog circuitry and digital functionality to co ? exist on the same chip. the ncv7420 lin device is a member of the in ? vehicle networking (ivn) transceiver family of on semiconductor that integrates a lin v2.0/2.1 physical transceiver and either a 3.3 v or a 5 v voltage regulator. it is designed to work in harsh automotive environment and is submitted to the ts16949 qualification flow. the lin bus is designed to communicate low rate data from control devices such as door locks, mirrors, car seats, and sunroofs at the lowest possible cost. the bus is designed to eliminate as much wiring as possible and is implemented using a single wire in each node. each node has a slave mcu ? state machine that recognizes and translates the instructions specific to that function. the main attraction of the lin bus is that all the functions are not time critical and usually relate to passenger comfort. key features lin ? bus transceiver ? lin compliant to specification revision 2.0 and 2.1 (backward compatible to version 1.3) and j2602 ? i3t high voltage technology ? bus voltage 45 v ? transmission rate up to 20 kbaud ? soic 14 green package ? this is a pb ? free device protection ? thermal shutdown ? indefinite short ? circuit protection on pins lin and wake towards supply and ground ? load dump protection (45 v) ? bus pins protected against transients in an automotive environment ? system esd protection level for lin, wake and vbb up to 12 kv emi compatibility ? integrated slope control ? meets most demanding ems/eme requirements voltage regulator ? output voltage 5 v / ~50 ma or 3.3 v / ~50 ma ? wake ? up input ? enable inputs for stand ? by and sleep mode ? inh output for auxiliary purposes (switching of an external pull ? up or resistive divider towards battery, control of an external voltage regulator etc.) modes ? normal mode: lin communication in either low (up to 10 kbaud) or normal slope ? sleep mode: v cc is switched ?off? and no communication on lin bus ? stand ? by mode: v cc is switched ?on? but there is no communication on lin bus ? wake ? up bringing the component from sleep mode into standby mode is possible either by lin command or digital input signal on wake pin. wake ? up from lin bus can also be detected and flagged when the chip is already in standby mode. quality ? automotive qualification according to aec ? q100, grade 1 soic 14 d suffix case 751ap http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 19 of this data sheet. ordering information 11 12 13 14 1 2 3 4 rxd txd stb wake lin v bb v cc ncv7420 5 6 7 10 9 8 gnd gnd otp_zap inh gnd en test pin configuration
ncv7420 http://onsemi.com 2 table 1. key technical characteristics ? 3.3 v version symbol parameter min typ max unit vbb nominal battery operating voltage (note 1) 5 12 26 v load dump protection (note 2) 45 ibb_slp supply current in sleep mode 20 a vcc_out (note 4) regulated vcc output, vcc load 1 ma ? 30 ma 3.23 3.30 3.37 v regulated vcc output, vcc load 0 ma ? 50 ma 3.19 3.30 3.41 iout_max maximum vcc output current (note 3) 50 ma v_wake operating dc voltage on wake pin 0 vbb v maximum rating voltage on wake pin ? 45 45 tj junction thermal shutdown temperature 165 195 c tjunc operating junction temperature ? 40 +150 c table 2. key technical characteristics ? 5 v version symbol parameter min typ max unit vbb nominal battery operating voltage (note 1) 6 12 26 v load dump protection 45 ibb_slp supply current in sleep mode 20 a vcc_out (note 4) regulated vcc output, vcc load 1 ma ? 30 ma 4.9 5.0 5.1 v regulated vcc output, vcc load 0 ma ? 50 ma 4.83 5.0 5.17 iout_max maximum vcc output current (note 3) 50 ma v_wake operating dc voltage on wake pin 0 vbb v maximum rating voltage on wake pin ? 45 45 tj junction thermal shutdown temperature 165 195 c tjunc operating junction temperature ? 40 +150 c 1. below 5 v on vbb in normal mode, the bus will either stay recessive or comply with the voltage level specifications and trans ition time specifications as required by sae j2602. it is ensured by the battery monitoring circuit. 2. the applied transients shall be in accordance with iso 7637 part 1, test pulse 5. the device complies with functional class c ; class a can be reached depending on the application and external conditions. 3. thermal aspects of the entire end ? application have to be taken into account in order to avoid thermal shutdown of ncv7420. 4. vcc voltage regulator output must be properly decoupled by external capacitor of min. 8 f with esr < 1 to ensure stability. table 3. thermal characteristics symbol parameter conditions value unit r th(vj ? a)_1 thermal resistance junction ? to ? ambient on jedec 1s0p pcb free air 140 k/w r th(vj ? a)_4 thermal resistance junction ? to ? ambient on jedec 2s2p pcb free air 80 k/w
ncv7420 http://onsemi.com 3 figure 1. block diagram stb txd en rxd wake control logic ncv7420 lin timeout driver & slope control thermal shutdown osc inh test otp_zap por v ? reg band ? gap receiver gnd normal mode stand ? by, sleep v bb v cc v bb v bb v cc v bb v cc v cc v cc typical application application schematic the emc immunity of the master ? mode device can be further enhanced by adding a capacitor between the lin output and ground. the optimum value of this capacitor is determined by the length and capacitance of the lin bus, the number and capacitance of slave devices, the pull ? up resistance of all devices (master & slave), and the required time constant of the system, respectively. vcc voltage must be properly stabilized by external capacitor: capacitor of min. 8 f (esr < 1 ).
ncv7420 http://onsemi.com 4 figure 2. typical application diagram kl30 lin ? bus kl31 lin master node 1 nf 1kw gnd ncv7420 micro controller gnd inh v bb vbat gnd 10nf wake lin slave node 220pf gnd micro controller vbat gnd wake 10uf v cc v cc 10uf 100nf test otp_zap 10nf gnd inh v bb v cc test otp_zap lin wake 10uf 100nf v cc lin wake en stb txd rxd ncv7420 en stb txd rxd 10uf table 4. pin description pin name description 1 vbb battery supply input 2 lin lin bus output/input 3 gnd ground 4 gnd ground 5 wake high voltage digital input pin to switch the part from sleep ? to standby mode 6 inh inhibit output 7 otp_zap supply for programming of trimming bits at factory testing, should be grounded in the application 8 test digital input for factory testing, should be grounded in the application 9 en enable input, transceiver in normal operation mode when high 10 stb standby mode control input 11 gnd ground 12 txd transmit data input, low in dominant state 13 rxd receive data output; low in dominant state; push ? pull output 14 vcc supply voltage (output) overall functional description lin is a serial communication protocol that efficiently supports the control of mechatronic nodes in distributed automotive applications. the domain is class ? a multiplex buses with a single master node and a set of slave nodes. ncv7420 is designed as a master or slave node for the lin communication interface with an integrated 3.3 v or 5 v voltage regulator having a current capability up to 50 ma for supplying any external components (microcontroller). ncv7420 contains the lin transmitter, lin receiver, voltage regulator, power ? on ? reset (por) circuits and thermal shutdown (tsd). the lin transmitter is optimized for the maximum specified transmission speed of 20 kbaud with emc performance due to reduced slew rate of the lin output. the junction temperature is monitored via a thermal shutdown circuit that switches the lin transmitter and voltage regulator off when temperature exceeds the tsd trigger level. ncv7420 has four operating states (normal mode, low slope mode, stand ? by mode, and sleep mode) that are determined by the input signals en, w ake, stb, and txd. operating states ncv7420 provides four operating states, two modes for normal operation with communication, one stand-by without communication and one low power mode with very low current consumption. see figure 3.
ncv7420 http://onsemi.com 5 figure 3. state diagram en goes from 0 to 1 while txd = 0, en goes from 1 to 0 en goes from 1 to 0 en goes from 0 to 1 while txd = 1, en goes from 1 to 0 power up vbb stand ? by mode normal mode (normal slope) sleep mode normal mode (low slope) power off and vcc > vcc_uv_th, vbb > vbb_uv_th while stb = 0 and vbb > vbb_uv_th while stb = 0 and vbb > vbb_uv_th vbb > vbb_uv_th vbb < porl_vbb and vcc > vcc_uv_th and vbb > vbb_uv_th from any mode while stb = 1 or vbb < vbb_uv_th while stb = 1 or vbb < vbb_uv_th local wake ? up or lin wake ? up note: lin transmitter is ?off? when vbb < vbb_uv_th en goes from 1 to 0 ? vcc: ?on? ? lin tx: ?off? ? term: ?current source? ? inh: ?floating? ? rxd: pull ? up to vcc/low ? vcc: ?on? ? lin tx: ?on? ? term: 30 k ? inh: ?high?/?floating? ? rxd: lin data (push ? pull) ? vcc: ?off? ? lin tx: ?off? ? term: ?current source? ? inh: ?floating? ? rxd: pull ? up to vcc ? vcc: ?on? ? lin tx: ?on? ? term: 30 k ? inh: ?high?/?floating? ? rxd: lin data (push ? pull) table 5. mode selection mode vcc rxd inh lin 30 k on lin note normal ? slope on low = dominant state high = recessive state high if stb=high during state transition; floating otherwise normal slope on (note 5) normal ? low slope on low = dominant state high = recessive state high if stb=high during state transition; floating otherwise low slope on (note 6) stand ? by on low after lin wakeup, high otherwise floating off off (notes 7 and 8) sleep off clamped to vcc floating off off 5. the normal slope mode is entered when pin en goes high while txd is in high state during en transition. 6. the low slope mode is entered when pin en goes high while txd is in low state during en transition. lin transmitter gets on o nly after txd returns to high after the state transition. 7. the stand ? by mode is entered automatically after power ? up. 8. in stand ? by mode, rxd high state is achieved by internal pull-up resistor to vcc. normal slope mode in normal slope mode the transceiver can transmit and receive data via lin bus with speed up to 20 kbaud. the transmit data stream of the lin protocol is present on the txd pin and converted by the transmitter into a lin bus signal with controlled slew rate to minimize emc emission. the receiver consists of the comparator that has a threshold with hysteresis in respect to the supply voltage and an input filter to remove bus noise. the lin output is pulled high via an internal 30 k pull-up resistor. for master applications it is needed to put an external 1 k resistor with a serial diode between lin and vbb (or inh). see figure 2. the mode selection is done by en=high when txd pin is high. if stb pin is high during the standby-to-normal slope mode transition, inh pin is pulled high. otherwise, it stays floating. low slope mode in low slope mode the slew rate of the signal on the lin bus is reduced (rising and falling edges of the lin bus signal are longer). this further reduces the emc emission. as a consequence the maximum speed on the lin bus is reduced up to 10 kbaud. this mode is suited for applications where the communication speed is not critical. the mode selection is done by en=high when txd pin is low. in order not to transmit immediately a dominant state on the bus (because
ncv7420 http://onsemi.com 6 txd=low), the lin transmitter is enabled only after txd returns to high. if stb pin is high during the standby ? to ? low slope mode transition, inh pin is pulled high. otherwise, it stays floating. stand ? by mode the stand ? by mode is always entered after power ? up of the ncv7420. it can also be entered from normal mode when the en pin is low and the stand ? by pin is high. from sleep mode it can be entered after a local wake ? up or lin wakeup. in stand ? by mode the vcc voltage regulator for supplying external components (e.g. a microcontroller) stays active. also the lin receiver stays active to be able to detect a remote wake ? up via bus. the lin transmitter is disabled and the slave internal termination resistor of 30 k between lin and vbb is disconnected in order to minimize current consumption. only a pull ? up current source between vbb and lin is active. sleep mode the sleep mode provides extreme low current consumption. this mode is entered when both en and stb pins are low coming from normal mode. the internal termination resistor of 30 k between lin and vbb is disconnected and also the vcc regulator is switched off to minimize current consumption. wake ? up ncv7420 has two possibilities to wake ? up from sleep or stand ? by mode (see figure 3): ? local wake ? up: enables the transition from sleep mode to stand ? by mode ? remote wake ? up via lin: enables the transition from sleep ? to stand ? by mode and can be also detected when already in standby mode. a local wake ? up is only detected in sleep mode if a transition from low to high or from high to low is seen on the wake pin. wake t v bb detection of local wake ? up sleep mode stand ? by mode 50% v bb typ. wake t v bb detection of local wake ? up sleep mode stand ? by mode 50% v bb typ. figure 4. local wake ? up signal a remote wake ? up is only detected if a combination of (1) a falling edge at the lin pin (transition from recessive to dominant) is followed by (2) a dominant level maintained for a time period > t wake and (3) again a rising edge at pin lin (transition from dominant to recessive) happens. lin recessive level lin t t wake 40% vbb detection of remote wake ? up v bb 60% vbb sleep mode stand ? by mode lin dominant level figure 5. remote wake ? up behavior the wake ? up source is distinguished by pin rxd in the stand ? by mode: ? rxd remains high after power ? up or local wake ? up. ? rxd is kept low until normal mode is entered after a remote wake ? up (lin).
ncv7420 http://onsemi.com 7 figure 6. operating modes transitions en stb txd power off stand ? by normal normal slope normal low slope stand ? by sleep vbb_uv_th wake ? up (local or lin) stand ? by power off porl_vbb v cc v bb
ncv7420 http://onsemi.com 8 electrical characteristics definitions all voltages are referenced to gnd (pin 11). positive currents flow into the ic. table 6. absolute maximum ratings ? 3.3 v and 5 v versions symbol parameter min max unit vbb battery voltage on pin vbb (note 9) ? 0.3 +45 v vcc dc voltage on pin vcc 0 +7 v i_vcc current delivered by the vcc regulator 50 ma v_lin lin bus voltage (note 10) ? 45 +45 v v_inh dc voltage on inhibit pin ? 0.3 vbb + 0.3 v v_wake dc voltage on wake pin ? 45 45 v v_dig_in dc input voltage on pins txd, rxd, en, stb ? 0.3 vcc + 0.3 v tjunc maximum junction temperature ? 40 +165 c vesd electrostatic discharge voltage on all pins; hbm (note 11) ? 2 +2 kv electrostatic discharge voltage on lin, inh, wake and vbb towards gnd; hbm (note 11) ? 4 +4 kv electrostatic discharge on lin, wake and vbb; system hbm (note 12) ? 8 +8 kv electrostatic discharge voltage on all pins; cdm (note 14) ? 500 +500 v vesd (emc/esd improved versions) electrostatic discharge voltage on all pins; hbm (note 11) ? 4 +4 kv electrostatic discharge voltage on lin, inh, wake and vbb towards gnd; hbm (note 11) ? 6 +6 kv electrostatic discharge on lin, wake and vbb; system hbm (note 13) ? 12 +12 kv electrostatic discharge voltage on all pins; cdm (note 14) ? 750 +750 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 9. the applied transients shall be in accordance with iso 7637 part 1, test pulses 1, 2, 3a, 3b, and 5. the device complies with functional class c; class a can be reached depending on the application and external components. 10. the applied transients shall be in accordance with iso 7637 part 1, test pulses 1, 2, 3a, and 3b. the device complies with f unctional class c; class a can be reached depending on the application and external components. 11. equivalent to discharging a 100 pf capacitor through a 1500 resistor. 12. equivalent to discharging a 150 pf capacitor through a 330 resistor conform to iec standard 61000 ? 4 ? 2. lin bus filter 220 pf, vbb blocking capacitor 100 nf, 3k3/10n r/c network on wake. 13. equivalent to discharging a 150 pf capacitor through a 330 resistor conform to iec standard 61000 ? 4 ? 2. no filter on lin, vbb blocking capacitor 100 nf, 3k3/10n r/c network on wake. 14. charged device model according esd-stm5.3.1.
ncv7420 http://onsemi.com 9 dc characteristics ? 3.3 v version (v bb = 5 v to 26 v; t junc = ? 40 c to +150 c; unless otherwise specified.) table 7. dc characteristics, supply ? pin vbb symbol parameter conditions min typ max unit ibb_on supply current normal mode; lin recessive 1.6 ma ibb_stb supply current stand ? by mode, vbb = 5?18 v, t junc < 105 c 70 a ibb_slp supply current sleep mode, vbb = 5?18 v, t junc < 105 c 20 a table 8. dc characteristics, voltage regulator ? pin vcc vcc_out regulator output voltage vcc load 1 ma ? 30 ma 3.23 3.30 3.37 v vcc load 0 ma ? 50 ma 3.19 3.30 3.41 iout_max_abs absolute maximum output current thermal shutdown must be taken into account 50 ma iout_lim over ? current limitation 50 100 170 ma vcc_out line regulation (note 20) vbb 5 ? 26 v, iout = 5 ma, tj = 25 c 0.5 mv load regulation (note 20) iout 1 ? 50 ma, vbb = 14 v, tj = 25 c 45 mv vdo dropout voltage (vbb ? vcc_out) figure 11, (notes 19, 20) iout = 1 ma, tj = 25 c 13 mv iout = 10 ma, tj = 25 c 134 mv iout = 50 ma, tj = 25 c 732 mv table 9. dc characteristics lin transmitter ? pin lin symbol parameter conditions min typ max unit vlin_dom_losup lin dominant output voltage txd = low; vbb = 7.3 v 1.2 v vlin_dom_hisup lin dominant output voltage txd = low; vbb = 18 v 2.0 v vser_diode lin voltage drop at serial diode (note 15) txd = high; ilin = 10 a 0.3 1 v ilin_lim short circuit current limitation vlin = vbb_max 40 200 ma rslave internal pull ? up resistance 20 33 47 k clin capacitance on pin lin (note 17) 15 25 pf ilin_off_dom lin output current bus in dominant state driver off; vbb = 12 v ? 1 ma ilin_off_rec lin output current bus in recessive state driver off; vbb < 18 v vbb < vlin < 18 v 1 a ilin_no_gnd communication not affected vbb = gnd = 12 v; 0 < vlin < 18 v ? 1 1 ma ilin_no_vbb lin bus remains operational vbb = gnd = 0 v; 0 < vlin < 18 v 5 a table 10. dc characteristics lin receiver ? pin lin symbol parameter conditions min typ max unit vbus_dom bus voltage for dominant state 0.4 vbb vbus_rec bus voltage for recessive state 0.6 vbb vrec_dom receiver threshold lin bus recessive dominant 0.4 0.6 vbb vrec_rec receiver threshold lin bus dominant recessive 0.4 0.6 vbb 15. the voltage drop in normal mode between lin and vbb pin is the sum of the diode drop and the drop at serial pull up resistor . the drop at the switch is negligible. see figure 1. 16. by one of the trimming bits, following reconfiguration can be done during chip ? level testing in order to fit the ncv7420_3 into different interface: pins txd and en will have typ. 10 k pull ? down resistor to ground and pin wake will have typ. 10 a pull ? up current source. 17. guaranteed by design. not tested. 18. vbb under ? voltage threshold is always higher than vbb por low level (vbb_uv_th > porl_vbb) 19. measured at output voltage vcc_out = (vcc_out@vbb = 5 v) ? 2%. 20. values based on design and characterization. not tested in production.
ncv7420 http://onsemi.com 10 dc characteristics ? 3.3 v version (v bb = 5 v to 26 v; t junc = ? 40 c to +150 c; unless otherwise specified.) table 10. dc characteristics lin receiver ? pin lin symbol unit max typ min conditions parameter vrec_cnt receiver centre voltage (vbus_dom + vbus_rec) / 2 0.475 0.525 vbb vrec_hys receiver hysteresis 0.05 0.175 vbb table 11. dc characteristics i/os symbol parameter conditions min typ max unit pin wake v_wake_th threshold voltage 0.35 0.65 vbb i_leak input leakage current (note 16) vwake = 0 v; vbb = 18 v ? 1 ? 0.5 1 a t_wake_min debounce time sleep mode; rising and falling edge 8 54 s pins txd and stb vil low level input voltage 0.8 v vih high level input voltage 2.0 v rpu pull ? up resistance to vcc (note 16) 50 200 k pin inh delta_vh high level voltage drop iinh = 15 ma 0.35 0.75 v i_leak leakage current sleep mode; vinh = 0 v ? 1 1 a pin en vil low level input voltage 0.8 v vih high level input voltage 2.0 v rpd pull ? down resistance to ground (note 16) 50 200 k pin rxd vol low level output voltage isink = 2 ma 0.65 v voh high level output voltage (in normal mode) normal mode, isource = ? 2 ma vcc ? 0.65 v v rpu pull ? up resistance to vcc (in standby and sleep mode) standby mode, sleep mode 5 10 15 k table 12. dc characteristics symbol parameter conditions min typ max unit por vbb_uv_th vbb under-voltage threshold (note 18) 3 4.2 4.75 v porl_vbb vbb por low level comparator ncv7420d23 2.5 4.2 v ncv7420d24 1.7 3.8 v vcc_uv_th vcc under-voltage threshold 2 3 v tsd tj junction temperature for shutdown 165 195 c tj_hyst thermal shutdown hysteresis 9 18 c 15. the voltage drop in normal mode between lin and vbb pin is the sum of the diode drop and the drop at serial pull up resistor . the drop at the switch is negligible. see figure 1. 16. by one of the trimming bits, following reconfiguration can be done during chip ? level testing in order to fit the ncv7420_3 into different interface: pins txd and en will have typ. 10 k pull ? down resistor to ground and pin wake will have typ. 10 a pull ? up current source. 17. guaranteed by design. not tested. 18. vbb under ? voltage threshold is always higher than vbb por low level (vbb_uv_th > porl_vbb) 19. measured at output voltage vcc_out = (vcc_out@vbb = 5 v) ? 2%. 20. values based on design and characterization. not tested in production.
ncv7420 http://onsemi.com 11 dc characteristics ? 5 v version ? (v bb = 6 v to 26 v; t junc = ? 40 c to +150 c; unless otherwise specified.) table 13. dc characteristics, supply ? pin vbb symbol parameter conditions min typ max unit ibb_on supply current normal mode; lin recessive 1.6 ma ibb_stb supply current stand ? by mode, vbb = 6?18 v, t junc < 105 c 70 a ibb_slp supply current sleep mode, vbb = 6?18 v, t junc < 105 c 20 a table 14. dc characteristics, voltage regulator ? pin vcc vcc_out regulator output voltage vcc load 1 ma ? 30 ma 4.9 5.0 5.1 v vcc load 0 ma ? 50 ma 4.83 5.0 5.17 iout_max_abs absolute maximum output current thermal shutdown must be taken into account 50 ma iout_lim over ? current limitation 50 100 170 ma vcc_out line regulation (note 26) vbb 6 ? 26 v, iout = 5 ma, tj = 25 c 0.9 mv load regulation (note 26) iout 1 ? 50 ma, vbb = 14 v, tj = 25 c 74 mv vdo dropout voltage (vbb ? vcc_out) figure 19 (notes 25, 26) iout = 1 ma, tj = 25 c 13 mv iout = 10 ma, tj = 25 c 136 mv iout = 50 ma, tj = 25 c 794 mv table 15. dc characteristics lin transmitter ? pin lin symbol parameter conditions min typ max unit vlin_dom_losup lin dominant output voltage txd = low; vbb = 7.3 v 1.2 v vlin_dom_hisup lin dominant output voltage txd = low; vbb = 18 v 2.0 v vser_diode lin voltage drop at serial diode (note 21) txd = high; ilin = 10 a 0.3 1 v ilin_lim short circuit current limitation vlin = vbb_max 40 200 ma rslave internal pull ? up resistance 20 33 47 k clin capacitance on pin lin (note 23) 15 25 pf ilin_off_dom lin output current bus in dominant state driver off; vbb = 12 v ? 1 ma ilin_off_rec lin output current bus in recessive state driver off; vbb < 18 v vbb < vlin < 18 v 1 a ilin_no_gnd communication not affected vbb = gnd = 12 v; 0 < vlin < 18 v ? 1 1 ma ilin_no_vbb lin bus remains operational vbb = gnd = 0 v; 0 < vlin < 18 v 5 a table 16. dc characteristics lin receiver ? pin lin symbol parameter conditions min typ max unit vbus_dom bus voltage for dominant state 0.4 vbb vbus_rec bus voltage for recessive state 0.6 vbb vrec_dom receiver threshold lin bus recessive dominant 0.4 0.6 vbb 21. the voltage drop in normal mode between lin and vbb pin is the sum of the diode drop and the drop at serial pull up resistor . the drop at the switch is negligible. see figure 1. 22. by one of the trimming bits, following reconfiguration can be done during chip ? level testing in order to fit the ncv7420_5 into different interface: pins txd and en will have typ. 10 k pull ? down resistor to ground and pin wake will have typ. 10 a pull ? up current source. 23. guaranteed by design. not tested. 24. vbb under ? voltage threshold is always higher than vbb por low level (vbb_uv_th > porl_vbb) 25. measured at output voltage vcc_out = (vcc_out@vbb = 6 v) ? 2%. 26. values based on design and characterization. not tested in production.
ncv7420 http://onsemi.com 12 dc characteristics ? 5 v version ? (v bb = 6 v to 26 v; t junc = ? 40 c to +150 c; unless otherwise specified.) symbol unit max typ min conditions parameter table 16. dc characteristics lin receiver ? pin lin vrec_rec receiver threshold lin bus dominant recessive 0.4 0.6 vbb vrec_cnt receiver center voltage (vbus_dom + vbus_rec) / 2 0.475 0.525 vbb vrec_hys receiver hysteresis 0.05 0.175 vbb table 17. dc characteristics i/os symbol parameter conditions min typ max unit pin wake v_wake_th threshold voltage 0.35 0.65 vbb i_leak input leakage current (note 22) vwake = 0 v; vbb = 18 v ? 1 ? 0.5 1 a t_wake_min debounce time sleep mode; rising and falling edge 8 54 s pins txd and stb vil low level input voltage 0.8 v vih high level input voltage 2.0 v rpu pull ? up resistance to vcc (note 22) 50 200 k pin inh delta_vh high level voltage drop iinh = 15 ma 0.35 0.75 v i_leak leakage current sleep mode; vinh = 0 v ? 1 1 a pin en vil low level input voltage 0.8 v vih high level input voltage 2.0 v rpd pull ? down resistance to ground (note 22) 50 200 k pin rxd vol low level output voltage isink = 2 ma 0.65 v voh high level output voltage (in normal mode) normal mode, isource = ? 2 ma vcc ? 0.65 v v rpu pull ? up resistance to vcc (in standby and sleep mode) standby mode, sleep mode 5 10 15 k table 18. dc characteristics symbol parameter conditions min typ max unit por vbb_uv_th vbb under-voltage threshold (note 24) 3 4.2 4.75 v porl_vbb vbb por low level comparator ncv7420d25 2.5 4.2 v ncv7420d26 1.7 3.8 v vcc_uv_th vcc under-voltage threshold 3 4.5 v tsd tj junction temperature for shutdown 165 195 c tj_hyst thermal shutdown hysteresis 9 18 c 21. the voltage drop in normal mode between lin and vbb pin is the sum of the diode drop and the drop at serial pull up resistor . the drop at the switch is negligible. see figure 1. 22. by one of the trimming bits, following reconfiguration can be done during chip ? level testing in order to fit the ncv7420_5 into different interface: pins txd and en will have typ. 10 k pull ? down resistor to ground and pin wake will have typ. 10 a pull ? up current source. 23. guaranteed by design. not tested. 24. vbb under ? voltage threshold is always higher than vbb por low level (vbb_uv_th > porl_vbb) 25. measured at output voltage vcc_out = (vcc_out@vbb = 6 v) ? 2%. 26. values based on design and characterization. not tested in production.
ncv7420 http://onsemi.com 13 ac characteristics ? 3.3 v and 5 v versions ? (v bb = 7 v to 18 v; t junc = ? 40 c to +150 c; unless otherwise specified.) table 19. ac characteristics lin transmitter ? pin lin symbol parameter conditions min typ max unit d1 duty cycle 1 = t bus_rec(min) / (2 x t bit ) see figure 23 normal slope mode th rec(max) = 0.744 x v bb th dom(max) = 0.581 x v bb t bit = 50 s v(v bb ) = 7 v to 18 v 0.396 0.5 d2 duty cycle 2 = t bus_rec(max) / (2 x t bit ) see figure 23 normal slope mode th rec(min) = 0.422 x v bb th dom(min) = 0.284 x v bb t bit = 50 s v(v bb ) = 7.6 v to 18 v 0.5 0.581 d3 duty cycle 3 = t bus_rec(min) / (2 x t bit ) see figure 23 normal slope mode th rec(max) = 0.778 x v bb th dom(max) = 0.616 x v bb t bit = 96 s v(v bb ) = 7 v to 18 v 0.417 0.5 d4 duty cycle 4 = t bus_rec(max) / (2 x t bit ) see figure 23 normal slope mode th rec(min) = 0.389 x v bb th dom(min) = 0.251 x v bb t bit = 96 s v(v bb ) = 7.6 v to 18 v 0.5 0.590 ttrx_prop_down propagation delay of txd to lin. txd high to low (note 27) 6 s ttrx_prop_up propagation delay of txd to lin. txd low to high (note 27) 6 s t_fall_norm lin falling edge normal slope mode; v bb = 12 v; l1, l2 (note 28) 22.5 s t_rise_norm lin rising edge normal slope mode; v bb = 12 v; l1, l2 (note 28) 22.5 s t_sym_norm lin slope symmetry normal slope mode; v bb = 12 v; l1, l2 (note 28) ? 4 4 s t_fall_norm lin falling edge normal slope mode; v bb = 12 v; l3 (note 28) 27 s t_rise_norm lin rising edge normal slope mode; v bb = 12 v; l3 (note 28) 27 s t_sym_norm lin slope symmetry normal slope mode; v bb = 12 v; l3 (note 28) ? 5 5 s t_fall_low lin falling edge low slope mode (note 29); v bb = 12 v; l3 (note 28) 62 s t_rise_low lin rising edge low slope mode (note 29); v bb = 12 v; l3 (note 28) 62 s t_wake dominant time ? out for wake ? up via lin bus 30 150 s t_dom txd dominant time ? out txd = low 6 20 ms 27. values based on design and characterization. not tested in production. 28. the ac parameters are specified for following rc loads on the lin bus: l1 = 1 k / 1 nf; l2 = 660 / 6.8 nf; l3 = 500 / 10 nf. 29. low slope mode is not compliant to the lin standard.
ncv7420 http://onsemi.com 14 regulator typical performance characteristics ? 3.3 v version load transient responses figure 7. load transient response (icc 100 a to 50 ma) figure 8. load transient response (icc 1 ma to 50 ma) time (500 s/div) time (500 s/div) 1 50 load current (ma) load current (ma) 0.1 50 v cc (20 mv/div) v cc (20 mv/div) t rise , t fall = 10 s v bb = 14 v c vbb = 10 f + 100 nf c vcc = 10 f x7r t rise , t fall = 10 s v bb = 14 v c vbb = 10 f + 100 nf c vcc = 10 f x7r line transient responses figure 9. line transient response (vbb 5 v to 26 v) figure 10. line transient response (vbb 5 v to 26 v) time (2 ms/div) time (1 ms/div) 10 30 input voltage (v) input voltage (v) 10 30 v cc (50 mv/div) v cc (20 mv/div) t rise , t fall = 10 s 0 20 0 20 i cc = 5 ma c vcc = 10 f t rise , t fall = 10 s i cc = 100 a c vcc = 10 f
ncv7420 http://onsemi.com 15 regulator typical performance characteristics ? 3.3 v version static characteristics figure 11. dropout voltage vs. temperature figure 12. output voltage vs. output current temperature ( c) icc output current (ma) 125 100 75 50 25 0 ? 25 ? 50 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 45 35 30 20 15 10 5 0 3.24 3.25 3.26 3.27 3.28 3.29 3.31 3.32 dropout voltage (v) vcc output voltage (v) 150 c vcc = 10 f x7r 50 ma 25 ma 10 ma 25 40 50 3.30 ? 40 c 25 c 85 c 135 c 150 c v bb = 14 v c vbb = 10 f + 100 nf c vcc = 10 f x7r (porl_vbb reached at low temperatures) figure 13. ground current vs. output current figure 14. output voltage vs. temperature icc output current (ma) temperature ( c) 45 35 30 25 20 10 5 0 0 20 60 80 100 140 160 200 125 100 75 50 25 0 ? 25 ? 50 3.24 3.25 3.26 3.27 3.28 3.30 3.31 3.32 ibb ? icc ( a) vcc output voltage (v) 15 40 50 40 120 180 v bb = 14 v c vbb = 10 f + 100 nf c vcc = 10 f x7r standby mode t = 25 c 150 3.29 50 ma 25 ma 10 ma 1 ma v bb = 14 v c vbb = 10 f + 100 nf c vcc = 10 f x7r
ncv7420 http://onsemi.com 16 regulator typical performance characteristics ? 5 v version load transient responses figure 15. load transient response (icc 100 a to 50 ma) figure 16. load transient response (icc 1 ma to 50 ma) time (500 s/div) time (500 s/div) 1 50 load current (ma) load current (ma) 0.1 50 v cc (50 mv/div) v cc (50 mv/div) t rise , t fall = 10 s v bb = 14 v c vbb = 10 f + 100 nf c vcc = 10 f x7r t rise , t fall = 10 s v bb = 14 v c vbb = 10 f + 100 nf c vcc = 10 f x7r line transient responses figure 17. line transient response (vbb 6 v to 26 v) figure 18. line transient response (vbb 6 v to 26 v) time (2 ms/div) time (1 ms/div) 10 30 input voltage (v) input voltage (v) 10 30 v cc (50 mv/div) v cc (20 mv/div) t rise , t fall = 10 s 0 20 0 20 i cc = 5 ma c vcc = 10 f t rise , t fall = 10 s i cc = 100 a c vcc = 10 f
ncv7420 http://onsemi.com 17 regulator typical performance characteristics ? 5 v version static characteristics figure 19. dropout voltage vs. temperature figure 20. output voltage vs. output current temperature ( c) icc output current (ma) 125 100 75 50 25 0 ? 25 ? 50 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 45 35 30 20 15 10 5 0 4.93 4.94 4.95 4.97 4.98 4.99 5.02 5.03 dropout voltage (v) vcc output voltage (v) 150 c vcc = 10 f x7r 50 ma 25 ma 10 ma 25 40 50 5.00 ? 40 c 25 c 85 c 135 c 150 c v bb = 14 v c vbb = 10 f + 100 nf c vcc = 10 f x7r 4.96 5.01 figure 21. ground current vs. output current figure 22. output voltage vs. temperature icc output current (ma) temperature ( c) 45 35 30 25 20 10 5 0 0 20 60 80 100 140 160 200 125 100 75 50 25 0 ? 25 ? 50 4.93 4.94 4.95 4.97 4.98 5.00 5.02 5.03 ibb ? icc ( a) vcc output voltage (v) 15 40 50 40 120 180 v bb = 14 v c vbb = 10 f + 100 nf c vcc = 10 f x7r standby mode t = 25 c 150 4.99 50 ma 25 ma 10 ma 1 ma v bb = 14 v c vbb = 10 f + 100 nf c vcc = 10 f x7r 4.96 5.01
ncv7420 http://onsemi.com 18 t bus_dom(min) lin t th rec(max) th rec(min) th dom(max) th dom(min) t bus_dom(max) t bus_rec(max) t bus_rec(min) t bit t bit 50% thresholds of receiving node 1 thresholds of receiving node 2 txd t figure 23. lin transmitter duty cycle figure 24. lin transmitter timing 50% txd lin t vbb 60% vbb 40% vbb t t trx_prop_up t trx_prop_down t bit t bit t_fall t_rise lin t 60% 40% 60% 40% 100% 0% figure 25. lin transmitter rising and falling times
ncv7420 http://onsemi.com 19 table 20. ac characteristics lin receiver symbol pin lin parameter conditions min typ max unit trec_prop_down propagation delay of receiver falling edge 0.1 6 s trec_prop_up propagation delay of receiver rising edge 0.1 6 s trec_sym propagation delay symmetry trec_prop_down ? trec_prop_up ? 2 2 s figure 26. lin receiver timing 50% t rec_prop_up rxd t lin t vbb 60% vbb 40% vbb t rec_prop_down ordering information part number description package container temperature range shipping ? qty ncv7420d23g lin transceiver + 3.3 v vreg. soic 150 14 green (jedec ms ? 012) tube/rail 55 ? 40 c to 125 c NCV7420D23R2G lin transceiver + 3.3 v vreg. soic 150 14 green (jedec ms ? 012) tape & reel 3000 ? 40 c to 125 c ncv7420d24g emc/esd improved lin transceiver + 3.3 v vreg. soic 150 14 green (jedec ms ? 012) tube/rail 55 ? 40 c to 125 c ncv7420d24r2g emc/esd improved lin transceiver + 3.3 v vreg. soic 150 14 green (jedec ms ? 012) tape & reel 3000 ? 40 c to 125 c ncv7420d25g lin transceiver + 5 v vreg. soic 150 14 green (jedec ms ? 012) tube/rail 55 ? 40 c to 125 c ncv7420d25r2g lin transceiver + 5 v vreg. soic 150 14 green (jedec ms ? 012) tape & reel 3000 ? 40 c to 125 c ncv7420d26g emc/esd improved lin transceiver + 5 v vreg. soic 150 14 green (jedec ms ? 012) tube/rail 55 ? 40 c to 125 c ncv7420d26r2g emc/esd improved lin transceiver + 5 v vreg. soic 150 14 green (jedec ms ? 012) tape & reel 3000 ? 40 c to 125 c ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncv7420 http://onsemi.com 20 package dimensions soic 14 case 751ap ? 01 issue a
ncv7420 http://onsemi.com 21 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncv7420/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative

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